Conventional process substrates with crystal orientation mark will be described by taking a semiconductor wafer as an example.
Conventionally, a semiconductor wafer is formed with an orientation flat or a notch for the purposes of its alignment during manufacturing processes and explicit indication of the in-plane crystal axis (orientation) of the wafer, (see, for example, paragraphs [0005] to [0006] of Japanese Patent Laid-Open No. 2011-3773). Here, orientation flat means a straight-line shaped outer edge portion formed in a semiconductor wafer. On the other hand, a notch means a cut formed in the vicinity of an outer edge portion of a semiconductor wafer.
Moreover, conventionally, it is also known that orientation flat is formed at two locations, thereby allowing the kind of wafer and the like to be distinguished (for example, see paragraph [0021] etc. of Japanese Patent Laid-Open No. H06-213652). In such a semiconductor wafer, it is possible to identify crystal plane orientations (generally, of three kinds: (100), (110), and (111) in the case of a silicon wafer) and the distinction between P-type/n-type of a wafer.
Further, as a method for discriminating the kind of semiconductor wafer and the like, there is also known a method of drawing with laser on a side face of the semiconductor wafer (see, for example, paragraph [0028] etc. of Japanese Patent Laid-Open No. H07-201688).
In a conventional semiconductor manufacturing technique, attempts have been made to reduce unit cost for manufacturing a chip by increasing the diameter of the semiconductor wafer. However, although such a large scale manufacturing system will contribute to reduction of unit cost for manufacturing a chip in a production of small-kinds in large quantities, it hardly responds to the demand of a production of many-kinds in small quantities, and makes it difficult to adjust the production quantities in response to market conditions, also making the market penetration by small businesses difficult. To solve these problems, it is desired to construct a manufacturing line using a small-scale semiconductor manufacturing apparatus which enables manufacturing of semiconductor chips at low cost using a small-diameter wafer (for example, a diameter of 0.5 inches) (see: Japanese Patent Laid-open No. 2012-54414). As one technical problem in promoting practical application and wide spreading of such a small-scale semiconductor manufacturing apparatus, the present inventors have studied on alignment technique of a small-diameter wafer and the like.
As a result of that, it has been revealed that in the case of a small-diameter wafer, it is necessary to form an orientation flat or a notch in a very small size, and therefore, it is difficult to realize a sufficiently accurate alignment inexpensively.
Moreover, it is also revealed that forming a small notch in a small-diameter wafer will take a lot of time and effort for surface finishing, and is against the demand for cost reduction in this respect as well.
Furthermore, a method of performing laser drawing to discriminate the kind of wafer and the like is also against the purpose of developing a small-diameter wafer as described above, since it is necessary to perform a laser drawing process in addition to the process of forming an orientation flat or a notch, thus causing increases in the cost and the number of processes.
Therefore, to perform alignment of wafer and identification of the kind thereof inexpensively with high precision for a small-diameter wafer, it is desirable to use a method different from the conventional orientation flat and notch.
It is an object of the present invention to provide at a low price a process substrate added with a crystal orientation mark which enables high precision alignment and allows information other than crystal orientation to be included, and also provide a method and an apparatus for detecting a crystal orientation by using such process substrate.